As semiconductor chip performance increases, the chip design becomes increasingly complex. Functionality from multiple chips is often integrated on a single chip as the ability to make more and smaller transistors improves. For example, the number of engines, such as central processing units (CPUs) and graphics processing units (GPUs), increases exponentially in successive technology generations. According to International Technology Roadmap for Semiconductors, in 2013 over two hundred engines are expected in one chip, increasing to over one thousand by 2020 and to over three thousand by 2024. The design of each of these engines and their relationships is verified by a design verification test prior to taping out the physical layout of the chip as a part of a path to launching a new product. An accurate and complete design verification test reduces the likelihood of product failure and can aid prototype test and debugging after manufacturing. As the number of engines, their complexity, and corresponding relationships become increasingly complex, the design verification test also becomes more time-consuming, labor-intensive, and resource-hungry.